The embodiments described below involve the field of microprocessors. Microprocessor-based computer systems have become incredibly prolific and are used at all levels of the public and private sector. With the vast increase of microprocessors in circulation has come increased design demands in many aspects of the microprocessor, including its reliability. In this regard, microprocessor manufacturers are known to test their microprocessors using various techniques before making the device available to a consumer. Such tests include testing of device design, and also specific tests for each individual integrated circuit before it is shipped. In these respects, therefore, considerable resources are devoted to such testing, and the present embodiments are directed to further improving various such testing activities.
For various integrated circuits, including microprocessors, testing is often used to address a known and generally accepted model for integrated circuit life span. Specifically, the model includes three periods of device reliability on a statistical basis over the life span of the device. In the first period, the model predicts that a certain percentage of integrated circuits will experience defects early in the life of the device, such as in its first few months to one year or so of normal operation. In the second period, it is anticipated that far fewer devices than those which experience problems during the first period will fail for an extensive period of time. Indeed, based on various considerations, the second period may extend up to ten years or more. Lastly, in the third period, the model predicts again that some devices will fail, with the amount of failures being considerably higher than those expected during the second term of the model.
One type of known testing to attempt to minimize the effect of the above model is known as burn-in. During the burn-in procedure, various device parameters are set to extremes beyond the normal operational specifications of the device. For example, input voltages may be increased to exceed, in absolute value, the specified operational limits of the device. As another example, the temperature to which the device is exposed also may be increased to exceed the specified operational limits for the device. Still other examples are known in the art. In any event, the burn-in procedure is believed to significantly shorten the duration of the first period of the above-discussed model. Thus, a particular device which may have failed after a year of normal operations is more likely to fail in a considerably shorter amount of time during burn-in As a result, a manufacturer may expose its integrated circuits to a burn-in period far shorter than the duration of the first period described above, and still identify many of those devices which would have failed over a greater period of time without the burn-in procedure. Consequently, the failed devices may then be removed from those which satisfactorily survive the burn-in procedure, thereby yielding a greater percentage of reliable devices for shipment to consumers.
In the context of microprocessors, another known type of testing to attempt to minimize the effect of the above model is to include some self-testing mechanism within the microprocessor. For example, a microprocessor typically includes a read only memory (ROM) for storing various programs for use in operating the microprocessor. Often, the ROM is referred to as a microROM and the programs it stores are sometimes referred to as microcode. Given this functionality, and in the context of testing, often a manufacturer includes one or more microcode programs in the microROM directed at testing the microprocessor. Alternatively, the testing operations may be implemented in some other on-device hardware. In any event, the test as a whole is sometimes referred to as a built-in self-test (BIST). The BIST is typically carried out at power-on or directed through some type of command such as during a scan test. Typically, the BIST checks more or less all chip components and, at the conclusion of the BIST, writes a code into a register. Thus, given that the duration of the BIST is known, the register may be examined at the end of the duration to determine whether the BIST completed and whether the device passed the checks performed by the BIST.
While the above approaches often assist in identifying defective microprocessors before those devices reach the market, the present inventors have identified various limitations of such techniques. For example, a failure during burn-in may require evaluation of numerous inputs and outputs of the device during the test. As another example, often BIST will only return a code at the end of the test and, therefore, there is no indication of the progression of the test before that end is reached. Moreover, even once the end of BIST is reached, the code (if any) resulting from a failure may not identify what caused the failure, or when during the BIST the failure occurred.
In view of the above, there arises a need to address the drawbacks of prior art testing techniques, as is accomplished by the embodiments provided below.